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SI9976DY
Vishay Siliconix
SI9976
N-Channel Half-Bridge Driver
FEATURES
* * * * * * * Single Input for High-Side and Low-Side MOSFETs 20- to 40-V Supply Static (dc) Operation Cross-Conduction Protected Undervoltage Lockout ESD and Short Circuit Protected Fault Feedback
APPLICATIONS
* * * * * * * Power Supplies Motor Drives Office Automation Computer Peripherals Industrial Controllers Robotics Medical Equipment
DESCRIPTION
The SI9976DY is an integrated driver for an n-channel MOSFET half-bridge. Schmitt trigger inputs provide logic signal compatibility and hysteresis for increased noise immunity. An internal low-voltage regulator allows the device to be powered directly from a system supply of 20 to 40 V. Both half-bridge n-channel gates are driven directly with low-impedance outputs. Addition of one external capacitor allows an internal circuit to level shift both the power supply and logic signal for the half-bridge high-side n-channel gate drive. An internal charge pump replaces leakage current lost in the high-side driver circuit to provide "static" (dc) operation in any output condition. Protection features include an undervoltage lockout, cross-conduction prevention logic, and a short circuit monitor. The SI9976DY is available in the 14-pin SOIC (surface mount) package, specified to operate over the industrial (-40 to 85C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
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S-60752-Rev. E, 05-Apr-99 1
SI9976DY
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltage on IN, EN (pins 5, 6) with respect to ground . . . . . . . . . . . . . . . . . . . . . . -0.3 to VDD +0.3 V Voltage on VCC (pin 7) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18 V Voltage on V+, S1 (pins 3, 13) . . . . . . . . . . . . . . . . . . . . -0.3 to +50 V Voltage on CAP, G1a (pins 2, 12) . . . . . . . . . . . . . . . . . . -0.3 to +60 V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 A Operating Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 to 150C Notes a. Internally generated voltage for reference only. b. Derate 10 mW/C above 25C. c. PC board mounted with no forced air flow. Maximum Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . 125C Power Dissipationb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W JA c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100C/W
SPECIFICATIONSa
Test Conditions UnlessOtherwise Specified Parameter Input
Input Voltage High (EN and IN) Input Voltage Low (EN and IN) Input Hysteresis Voltage Input Curren---Input Voltage High Input Current--Input Voltage Low VINH VINL VH IINH IINL (EN and IN) VIN = 15 V (EN and IN) VIN = 0 V -1 0.5 1 A 4.0 1.0 V
Limits
D Suffix -40 to 85C
Symbol
V+ = 20 to 40 V TA = Operating Temperature Range
Minc
Typb
Maxc
Unit
Output
Output Voltage High, G1d Output Voltage High, G2e Output Voltage Low, G1 and G2 Fault Output Voltage High Fault Output Voltage Low Undervoltage Lockout 1 Undervoltage Lockout 2 Capacitor Voltageg Capacitor Current VOUTH VOUTL VOH VOL UVL1 UVL2 VCAP ICAP V+ = 40V S1 = GND, VCAP = 0 V S1 = GND, VCAP = 9 V S1 = V+, IOUT = -10 mA S1 = GND, IOUT = -10 mA S1 = GND, IOUT = 60 mA VCC = 4.5 V, IOUT = -0.2 mA VCC = 4.5 V, IOUT = 0.6 mA 3.5 10 12 12 15 1.2 4 0.3 11 14 55 -10 -2 mA 1.0 3 V
Supply
V+ Supply Range V+ Supply Current VCC Supply Range VCC Supply Current VDD Supply Voltagef ICC VDD VCC = 16.5 V 15 16 I+ (H) I+ (L) G2 High, No Load G2 Low, No Load, S1 = GND 4.5 20 1.7 2 40 3.5 4.5 16.5 10 17.5 V mA V A V
S-60752-Rev. E, 05-Apr-99 2
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SI9976DY
Vishay Siliconix
SPECIFICATIONSa
Test Conditions UnlessOtherwise Specified Parameter Dynamic
Propogation Delay Time Low to High Level Propogation Delay Time High to Low Level Propogation Delay Time, Low to High Level, Enable-to-Fault Output Output Rise Time (G1, G2) Output Fall Time (G1, G2) Short Circuit Pulse Width Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. d. To supply the output current of 10 mA on a dc basis, an external 13-V supply must be connected between the CAP pin and the S1 pin with the negative terminal of the supply connected to S1. This is not needed in an actual application because output currents are supplied by the CBOOT capacitor. Voltage specified with respect to V+. e. For testing purposes, the 10-mA load current must be supplied by an external current source to the VDD pin to avoid pulling down the VDD supply. f. Internally generated voltage for reference only. g. VCAP = (V+) + (VDD) tr tf tSC tPLH 50% IN to VOUT = 5 V, CL = 600 pF tPHL 50% IN to FAULT = 2 V, S1 shorted to GND or V+ 1 to 10 V, CL = 600 pf 10 to 1 V, CL = 600 pf 50% to 50% of VOUT G1 G2 G1 G2 350 400 150 50 500 110 50 350 ns
Limits
D Suffix -40 to 85C
Symbol
V+ = 20 to 40 V TA = Operating Temperature Range
Minc
Typb
Maxc
Unit
TRUTH TABLE
EN
1 1 0 1 1 1 1 X Notes a. FAULT output retains previous state until ENABLE rising edge. b. Latch FAULT condition, reset by ENABLE rising edge. c. VDD is an internally generated low-voltage supply
IN
0 1 X 0 1 1 0 X
Condition
Normal Operation Normal Operation Disabled Load Shorted to V+ Load Shorted to Ground Undervoltage on CBOOT Undervoltage on CBOOT Undervoltage on VDDc
FAULT OUTPUT
0 0 X
a
G1 OUT
Low High Low Low Low Low Low Low
G2 OUT
High Low Low Low Low Low High Low
1b 1b 0 0 1
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SI9976DY
Vishay Siliconix
PIN DESCRIPTION
Pin 1 No connection. Pin 2: CAP Connection for the positive terminal of the bootstrap capacitor CBOOT. A 0.01-F CBOOT capacitor can be used for most applications. Pin 3: V+ This is the only external power supply required for the SI9976DY, and must be the same supply used to power the half-bridge it is driving. The SI9976DY powers it's low-voltage logic, low-side gate driver, and bootstrap/charge pump circuits from self-contained voltage regulators which require only a bootstrap capacitor on the CAP pin and a bypass capacitor on the VDD pin. No voltage sensing circuitry monitors V+ directly; however, the low-voltage, internally generated VDD supply and the bootstrap voltage (which are derived from V+) are directly protected by undervoltage monitors. Pin 4: VDD Connection to the internally generated low-voltage supply which must be bypassed to ground with a 0.01-F capacitor. Pin 5: IN Logic input. A low level input turns off the high-side half-bridge MOSFET and, after an internally set dead time, turns the low-side half-bridge MOSFET on. A high input level has the opposite effect. The input is compatible with 5-, 12- or 15-V logic outputs. Pin 6: EN Enable input. A low EN input level prevents turn on of either half-bridge MOSFET. If the SI9976DY is internally disabled as a result of an output short-circuit condition, a low-to-high transition on EN is required to clear the fault and resume operation. The input logic levels are the same as IN. Pin 7: VCC If the FAULT output is used, the VCC pin must be connected to the logic supply voltage in order to set the high level of the FAULT output. If the FAULT output is not used, this pin may be left open with no effect on internal fault sensing or protection circuitry. Pin 8: FAULT The Fault output is latched high when a short-circuit output condition is detected. FAULT will return low when the circuit is reset using the EN pin. The FAULT output also indicates the status of the undervoltage sense circuit on VDD, however the fault condition is cleared automatically when the undervoltage condition clears. Pin 9: G2 This pin drives the gate of the external low-side power transistor. Pin 10: GND The ground return for V+, logic reference, and connection for source of external low-side power transistor. Pin 11 No connection. Pin 12: G1 This pin drives the gate of the external high side power transistor. Pin 13: S1 Connection for the source of the external high-side power transistor, the drain of the external low-side power transistor, the negative terminal of the bootstrap capacitor, and the system load. The voltage on this pin is sensed by the circuitry that monitors the load for shorts. Pin 14 No connection.
S-60752-Rev. E, 05-Apr-99 4
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SI9976DY
Vishay Siliconix
DETAILED DESCRIPTION
Power On Conditioning Bootstrap-type floating supplies require that the bootstrap capacitor be charged at power on. In the case of the SI9976DY, this is accomplished by pulsing the IN line low with the EN line held high, thus turning on the low-side MOSFET and providing the charging path for the capacitor. Operating Voltage: 20 to 40 V The SI9976DY is intended to be powered by a single power supply within the range of 20 to 40 V and is designed to drive a totem pole pair of NMOS power transistors such as those within the Si9955. The power transistors must be powered by the same power supply as this driver. In addition to the high-voltage power supply (20 to 40 V), the SI9976DY must have a power supply connected to the VCC terminal, if a fault output signal is desired. This power supply provides operating voltage for the fault output and allows the high output voltage level to be compatible with system logic that monitors the fault condition. The value of this power supply must be within the range of 4.5 to 16.5 V to ensure functionality of the output. Internal fault circuitry, which is used for shorted-load protection, is not affected by this power supply. Cross-Conduction Protection The high-side power transistor can only be turned on after a fixed time delay following the return to ground of the low-side power transistor's gate. The low-side transistor can only be turned on after a fixed time delay following the high-side transistor turn-off signal. Undervoltage Lockout During power up, both power transistors are held off until the internal regulated power supply, VDD, is approximately one Vbe from the final value, nominally 16 V. After power up, the undervoltage lockout circuitry continues to monitor VDD. If an undervoltage condition occurs, both the high-side and low-side transistors will be turned off and the fault output will be set high. When the undervoltage condition no longer exists, normal function will resume automatically. Separate voltage sensing of the bootstrap capacitor voltage allows a turn-on signal to be sent to the high-side drive circuit if either the bootstrap capacitor has full voltage, or the load voltage is high (driven high by an inductive load or shorted high). The voltage sensing circuit will allow the high-side power transistor to turn on if an on signal is present and the voltage on the bootstrap capacitor rises from undervoltage to operating voltage. Short Circuit Protection This device is intended to be used only in a half-bridge which drives inductive loads. A shorted load is presumed if the load voltage does not make the intended transition within an allotted time. Separate timing is provided for the two transitions. A longer time is allowed for the high-side to turn on (300 ns vs. 200 ns) since the propagation delays are longer. Excessive capacitive loading can be interpreted as a short. The value of capacitance that is needed to produce the indication of a short depends on the load driving capability of the power transistors. ESD Protection Electrostatic discharge protection devices are between VDD and GND, VCC and GND, and from terminals IN, EN, G2, and FAULT to both VDD and GND. V+, CAP, S1, and G1 are not ESD protected. Fault Feedback Detection of a shorted load sets a latch which turns off both the high-side and the low-side power transistors. If VCC is present, a one level will be present on the FAULT output. To reset the system, the enable input, EN, must be lowered to a logic zero and then raised to a logic one. The logic level of the input, IN, will determine which power transistor will be turned on first after reset. An undervoltage condition on VDD is not latched, but causes a one level on the FAULT output, if VCC is present. Static (dc) Operation All components of a charge pump, except the holding (bootstrap) capacitor, are included in the circuit. This charge pump will provide current that is sufficient to overcome any leakage currents which would reduce the enhancement voltage of the high-side power transistor while it is on. This allows the high-side power transistor to be on continuously. When the low-side power transistor is turned on, additional charge is restored to the bootstrap capacitor, if needed. The maximum switching speed of the system at 50% duty cycle is limited by the on time of the low-side power transistor. During this time, the bootstrap capacitor charge must be restored. However, if the duty cycle is skewed so that the on time of the high-side power transistor is long enough for the charge pump to completely restore the charge lost during switching, then the on time of the low-side power transistor is not restricted.
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